BibTeX record conf/vlsic/ZhangZY19

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@inproceedings{DBLP:conf/vlsic/ZhangZY19,
  author       = {Zhao Zhang and
                  Guang Zhu and
                  C. Patrick Yue},
  title        = {A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz {PLL} Using an Offset Dual-Path
                  Loop Architecture with Dynamic Charge Pumps},
  booktitle    = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
  pages        = {158},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.23919/VLSIC.2019.8778061},
  doi          = {10.23919/VLSIC.2019.8778061},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/ZhangZY19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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