BibTeX record conf/vlsic/YuanYYW0YGLCYL18

• > Home > conf/vlsic/YuanYYW0YGLCYL18

@inproceedings{DBLP:conf/vlsic/YuanYYW0YGLCYL18,
  author       = {Zhe Yuan and
                  Jinshan Yue and
                  Huanrui Yang and
                  Zhibo Wang and
                  Jinyang Li and
                  Yixiong Yang and
                  Qingwei Guo and
                  Xueqing Li and
                  Meng{-}Fan Chang and
                  Huazhong Yang and
                  Yongpan Liu},
  title        = {Sticker: {A} 0.41-62.1 {TOPS/W} 8Bit Neural Network Processor with
                  Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration
                  for Fully Connected Layers},
  booktitle    = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
                  18-22, 2018},
  pages        = {33--34},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/VLSIC.2018.8502404},
  doi          = {10.1109/VLSIC.2018.8502404},
  timestamp    = {Mon, 27 Mar 2023 16:39:55 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/YuanYYW0YGLCYL18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}