BibTeX record conf/vlsic/XuOI21

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@inproceedings{DBLP:conf/vlsic/XuOI21,
  author       = {Zule Xu and
                  Masaru Osada and
                  Tetsuya Iizuka},
  title        = {A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling
                  {PLL} Using CDAC-Embedded Digital Integral Path with -80-dBc Reference
                  Spur},
  booktitle    = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.23919/VLSICircuits52068.2021.9492381},
  doi          = {10.23919/VLSICIRCUITS52068.2021.9492381},
  timestamp    = {Mon, 02 Aug 2021 16:53:09 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/XuOI21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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