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BibTeX record conf/vlsic/ShihLCLLCLYYCCC18
@inproceedings{DBLP:conf/vlsic/ShihLCLLCLYYCCC18, author = {Yi{-}Chun Shih and Chia{-}Fu Lee and Yen{-}An Chang and Po{-}Hao Lee and Hon{-}Jarn Lin and Yu{-}Lin Chen and Ku{-}Feng Lin and Ta{-}Ching Yeh and Hung{-}Chang Yu and Harry Chuang and Yu{-}Der Chih and Tsung{-}Yung Jonathan Chang}, title = {Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-{\(\mu\)}A Sensing Resolution, and 17.5NS Read Access Time}, booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June 18-22, 2018}, pages = {79--80}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/VLSIC.2018.8502260}, doi = {10.1109/VLSIC.2018.8502260}, timestamp = {Wed, 07 Apr 2021 09:24:20 +0200}, biburl = {https://dblp.org/rec/conf/vlsic/ShihLCLLCLYYCCC18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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