BibTeX record conf/vlsic/NamuraKAIKKWTKM21

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@inproceedings{DBLP:conf/vlsic/NamuraKAIKKWTKM21,
  author       = {Ken Namura and
                  Johannes Maximilian K{\"{u}}hn and
                  Tohru Adachi and
                  H. Imachi and
                  H. Kaneko and
                  T. Kato and
                  Go Watanabe and
                  Naoto Tanaka and
                  S. Kashihara and
                  Hiroshi Miyashita and
                  Y. Tomonaga and
                  Ryosuke Okuta and
                  Takuya Akiba and
                  Brian Vogel and
                  S. Kitajo and
                  F. Osawa and
                  K. Takahashi and
                  Y. Takatsukasa and
                  K. Mizumaru and
                  T. Yamauchi and
                  J. Ono and
                  A. Takahashi and
                  Tanvir Ahmed and
                  Y. Doi and
                  K. Hiraki and
                  J. Makino},
  title        = {MN-Core - {A} Highly Efficient and Scalable Approach to Deep Learning},
  booktitle    = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.23919/VLSICircuits52068.2021.9492395},
  doi          = {10.23919/VLSICIRCUITS52068.2021.9492395},
  timestamp    = {Fri, 11 Feb 2022 16:53:29 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsic/NamuraKAIKKWTKM21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}