BibTeX record conf/vlsic/DeshpandeGJNK21

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@inproceedings{DBLP:conf/vlsic/DeshpandeGJNK21,
  author       = {Chetan Deshpande and
                  Ritesh Garg and
                  Gajanan Jedhe and
                  Gaurang Narvekar and
                  Sushil Kumar},
  title        = {A 5nm Fin-FET 2G-search/s 512-entry x 220-bit {TCAM} with Single Cycle
                  Entry Update Capability for Data Center ASICs},
  booktitle    = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.23919/VLSICircuits52068.2021.9492464},
  doi          = {10.23919/VLSICIRCUITS52068.2021.9492464},
  timestamp    = {Mon, 02 Aug 2021 16:53:09 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/DeshpandeGJNK21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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