BibTeX record conf/vlsic/CakirCCTMTSB19

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@inproceedings{DBLP:conf/vlsic/CakirCCTMTSB19,
  author       = {Cagla Cakir and
                  Andy W. Chen and
                  Y. K. Chong and
                  Sriram Thyagarajan and
                  Mark P. McCartney and
                  Peixuan Tan and
                  Yulin Shi and
                  Mudit Bhargava},
  title        = {A 4GHz 16nm {SRAM} Architecture with Low-Power Features for Heterogeneous
                  Computing Platforms},
  booktitle    = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
  pages        = {112},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.23919/VLSIC.2019.8778108},
  doi          = {10.23919/VLSIC.2019.8778108},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/CakirCCTMTSB19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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