Power invariant secure IC design methodology using reduced complementary dynamic and differential logic.

Vijay Sundaresan Srividhya Rammohan Ranga Vemuri Power invariant secure IC design methodology using reduced complementary dynamic and differential logic. 1-6 2007 VLSI-SoC http://dx.doi.org/10.1109/VLSISOC.2007.4402463 conf/vlsi/2007soc db/conf/vlsi/vlsisoc2007.html#SundaresanRV07