BibTeX record conf/vlsi/RoviniGRF07

download as .bib file

@inproceedings{DBLP:conf/vlsi/RoviniGRF07,
  author       = {Massimo Rovini and
                  Giuseppe Gentile and
                  Francesco Rossi and
                  Luca Fanucci},
  title        = {A minimum-latency block-serial architecture of a decoder for {IEEE}
                  802.11n {LDPC} codes},
  booktitle    = {{IFIP} VLSI-SoC 2007, {IFIP} {WG} 10.5 International Conference on
                  Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA,
                  15-17 October 2007},
  pages        = {236--241},
  publisher    = {{IEEE}},
  year         = {2007},
  url          = {https://doi.org/10.1109/VLSISOC.2007.4402504},
  doi          = {10.1109/VLSISOC.2007.4402504},
  timestamp    = {Wed, 07 Dec 2022 23:11:42 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsi/RoviniGRF07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.