BibTeX record conf/vlsi/ParkSL15a

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@inproceedings{DBLP:conf/vlsi/ParkSL15a,
  author       = {Jaehyun Park and
                  Donghwa Shin and
                  Hyung Gyu Lee},
  title        = {Design space exploration of row buffer architecture for phase change
                  memory with {LPDDR2-NVM} interface},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {104--109},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314400},
  doi          = {10.1109/VLSI-SOC.2015.7314400},
  timestamp    = {Mon, 19 Dec 2022 20:39:10 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsi/ParkSL15a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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