Silicide Optimization for Electrostatic Discharge Protection Devices in Sub-100 nm CMOS Circuit Design.

Jam Wem Lee Yiming Li Howard Tang Silicide Optimization for Electrostatic Discharge Protection Devices in Sub-100 nm CMOS Circuit Design. 251-260 2003 conf/vlsi/2003 VLSI db/conf/vlsi/vlsi2003.html#LeeLT03