Cyrus Bazeghi Francisco J. Mesa-Martinez Brian Greskamp Josep Torrellas Jose Renau Estimating design time for system circuits. 60-65 2007 VLSI-SoC http://dx.doi.org/10.1109/VLSISOC.2007.4402473 conf/vlsi/2007soc db/conf/vlsi/vlsisoc2007.html#BazeghiMGTR07