4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR.

Nazrul Anuar Yasuhiro Takahashi Toshikazu Sekine 4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. 364-368 2010 VLSI-SoC http://dx.doi.org/10.1109/VLSISOC.2010.5642688 conf/vlsi/2010soc db/conf/vlsi/vlsisoc2010.html#AnuarTS10