BibTeX record conf/vlsi-dat/HsuLH19

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@inproceedings{DBLP:conf/vlsi-dat/HsuLH19,
  author       = {Pai{-}Hsiang Hsu and
                  Yueh{-}Ru Lee and
                  Chung{-}Chih Hung},
  title        = {10-Bit {SAR} {ADC} With Novel Pseudo-Random Capacitor Switching Scheme},
  booktitle    = {International Symposium on {VLSI} Design, Automation and Test, {VLSI-DAT}
                  2019, Hsinchu, Taiwan, April 22-25, 2019},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/VLSI-DAT.2019.8741534},
  doi          = {10.1109/VLSI-DAT.2019.8741534},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi-dat/HsuLH19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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