BibTeX record conf/vlsi-dat/ChenHL15

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@inproceedings{DBLP:conf/vlsi-dat/ChenHL15,
  author       = {Yu{-}Chuan Chen and
                  Chih{-}Cheng Hsu and
                  Mark Po{-}Hung Lin},
  title        = {Low-power gated clock tree optimization for three-dimensional integrated
                  circuits},
  booktitle    = {{VLSI} Design, Automation and Test, {VLSI-DAT} 2015, Hsinchu, Taiwan,
                  April 27-29, 2015},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-DAT.2015.7114530},
  doi          = {10.1109/VLSI-DAT.2015.7114530},
  timestamp    = {Sun, 12 Nov 2023 02:16:38 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsi-dat/ChenHL15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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