BibTeX record conf/vdat/WarisMKMC15

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@inproceedings{DBLP:conf/vdat/WarisMKMC15,
  author       = {Mohammad Waris and
                  Urvi Mehta and
                  Rajiv Kumaran and
                  Sanjeev Mehta and
                  Arup Roy Chowdhury},
  title        = {An all digital delay lock loop architecture for high precision timing
                  generator},
  booktitle    = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
                  Ahmedabad, India, June 26-29, 2015},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2015},
  url          = {https://doi.org/10.1109/ISVDAT.2015.7208138},
  doi          = {10.1109/ISVDAT.2015.7208138},
  timestamp    = {Fri, 24 Mar 2023 00:03:43 +0100},
  biburl       = {https://dblp.org/rec/conf/vdat/WarisMKMC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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