BibTeX record conf/vdat/MaheshwaramPSBM17

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@inproceedings{DBLP:conf/vdat/MaheshwaramPSBM17,
  author       = {Satish Maheshwaram and
                  Om. Prakash and
                  Mohit Sharma and
                  Anand Bulusu and
                  Sanjeev Manhas},
  editor       = {Brajesh Kumar Kaushik and
                  Sudeb Dasgupta and
                  Virendra Singh},
  title        = {Vertical Nanowire {FET} Based Standard Cell Design Employing Verilog-A
                  Compact Model for Higher Performance},
  booktitle    = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
                  Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series       = {Communications in Computer and Information Science},
  volume       = {711},
  pages        = {239--248},
  publisher    = {Springer},
  year         = {2017},
  url          = {https://doi.org/10.1007/978-981-10-7470-7\_24},
  doi          = {10.1007/978-981-10-7470-7\_24},
  timestamp    = {Thu, 17 Aug 2023 07:50:50 +0200},
  biburl       = {https://dblp.org/rec/conf/vdat/MaheshwaramPSBM17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}