BibTeX record conf/vdat/DheepikaJCK17

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@inproceedings{DBLP:conf/vdat/DheepikaJCK17,
  author       = {K. Dheepika and
                  K. S. Jevasankari and
                  Vippin Chandhar and
                  Binsu J. Kailath},
  editor       = {Brajesh Kumar Kaushik and
                  Sudeb Dasgupta and
                  Virendra Singh},
  title        = {Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder},
  booktitle    = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
                  Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series       = {Communications in Computer and Information Science},
  volume       = {711},
  pages        = {36--47},
  publisher    = {Springer},
  year         = {2017},
  url          = {https://doi.org/10.1007/978-981-10-7470-7\_4},
  doi          = {10.1007/978-981-10-7470-7\_4},
  timestamp    = {Tue, 29 Dec 2020 18:38:29 +0100},
  biburl       = {https://dblp.org/rec/conf/vdat/DheepikaJCK17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}