BibTeX record conf/socc/VermaTSJ15

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@inproceedings{DBLP:conf/socc/VermaTSJ15,
  author       = {Vaibhav Verma and
                  Sachin Taneja and
                  Pritender Singh and
                  Sanjeev Kumar Jain},
  title        = {A 128-kb 10{\%} power reduced 1T high density {ROM} with 0.56 ns access
                  time using bitline edge sensing in sub 16nm bulk FinFET technology},
  booktitle    = {28th {IEEE} International System-on-Chip Conference, {SOCC} 2015,
                  Beijing, China, September 8-11, 2015},
  pages        = {304--309},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/SOCC.2015.7406972},
  doi          = {10.1109/SOCC.2015.7406972},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/VermaTSJ15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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