BibTeX record conf/socc/NimbekarVDSGCA22

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@inproceedings{DBLP:conf/socc/NimbekarVDSGCA22,
  author       = {Anagha Nimbekar and
                  Chandrasekhara Srinivas Vatti and
                  Y. V. Sai Dinesh and
                  Sunidhi Singh and
                  Tarun Gupta and
                  Ramesh Reddy Chandrapu and
                  Amit Acharyya},
  editor       = {Sakir Sezer and
                  Thomas B{\"{u}}chner and
                  J{\"{u}}rgen Becker and
                  Andrew Marshall and
                  Fahad Siddiqui and
                  Tanja Harbaum and
                  Kieran McLaughlin},
  title        = {Low Complexity Reconfigurable-Scalable Architecture Design Methodology
                  for Deep Neural Network Inference Accelerator},
  booktitle    = {35th {IEEE} International System-on-Chip Conference, {SOCC} 2022,
                  Belfast, United Kingdom, September 5-8, 2022},
  pages        = {1--6},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/SOCC56010.2022.9908073},
  doi          = {10.1109/SOCC56010.2022.9908073},
  timestamp    = {Sat, 30 Sep 2023 09:57:04 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/NimbekarVDSGCA22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}