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BibTeX record conf/smacd/Ponce-Hinestroza18
@inproceedings{DBLP:conf/smacd/Ponce-Hinestroza18, author = {Vicente Yair Ponce{-}Hinestroza and Victor R. Gonzalez{-}Diaz}, title = {System-Level Behavioral Model of a 12-Bit 1.5-Bit Per Stage Pipelined {ADC} Based on Verilog\({}^{\mbox{{\textregistered}}}\)=-AMS}, booktitle = {15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, {SMACD} 2018, Prague, Czech Republic, July 2-5, 2018}, pages = {301--304}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/SMACD.2018.8434881}, doi = {10.1109/SMACD.2018.8434881}, timestamp = {Sun, 19 Sep 2021 11:41:51 +0200}, biburl = {https://dblp.org/rec/conf/smacd/Ponce-Hinestroza18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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