Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.

Valavan Manohararajah Gordon R. Chiu Deshanand P. Singh Stephen Dean Brown Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. 3-8 2006 conf/slip/2006 SLIP http://doi.acm.org/10.1145/1117278.1117280 db/conf/slip/slip2006.html#ManohararajahCSB06