<?xml version="1.0"?>
<dblp>
<inproceedings key="conf/slip/MakDSCYL08" mdate="2008-05-05">
<author>Terrence S. T. Mak</author>
<author>Crescenzo D'Alessandro</author>
<author>N. Pete Sedcole</author>
<author>Peter Y. K. Cheung</author>
<author>Alexandre Yakovlev</author>
<author>Wayne Luk</author>
<title>Global interconnections in FPGAs: modeling and performance analysis.</title>
<pages>51-58</pages>
<year>2008</year>
<booktitle>SLIP</booktitle>
<ee>http://doi.acm.org/10.1145/1353610.1353621</ee>
<crossref>conf/slip/2008</crossref>
<url>db/conf/slip/slip2008.html#MakDSCYL08</url>
</inproceedings>
</dblp>
