BibTeX record conf/slip/JevticCP09

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@inproceedings{DBLP:conf/slip/JevticCP09,
  author       = {Ruzica Jevtic and
                  Carlos Carreras and
                  Vukasin Pejovic},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Floorplan-based {FPGA} interconnect power estimation in {DSP} circuits},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {53--60},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572481},
  doi          = {10.1145/1572471.1572481},
  timestamp    = {Mon, 26 Jun 2023 20:48:05 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/JevticCP09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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