BibTeX record conf/sips/TehraniMG07

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@inproceedings{DBLP:conf/sips/TehraniMG07,
  author       = {Saeed Sharifi Tehrani and
                  Shie Mannor and
                  Warren J. Gross},
  title        = {An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic
                  {LDPC} Decoding},
  booktitle    = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
                  2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China},
  pages        = {255--260},
  publisher    = {{IEEE}},
  year         = {2007},
  url          = {https://doi.org/10.1109/SIPS.2007.4387554},
  doi          = {10.1109/SIPS.2007.4387554},
  timestamp    = {Thu, 14 Oct 2021 10:18:14 +0200},
  biburl       = {https://dblp.org/rec/conf/sips/TehraniMG07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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