Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories.

Wei Liu Junrye Rho Wonyong Sung Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories. 303-308 2006 SiPS http://dx.doi.org/10.1109/SIPS.2006.352599 conf/sips/2006 db/conf/sips/sips2006.html#LiuRS06