BibTeX record conf/sips/HsuC11a

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@inproceedings{DBLP:conf/sips/HsuC11a,
  author       = {Po{-}Hao Hsu and
                  Shao{-}Yi Chien},
  title        = {Reconfigurable cache memory architecture for integral image and integral
                  histogram applications},
  booktitle    = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
                  2011, October 4-7, 2011, Beirut, Lebanon},
  pages        = {151--156},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/SiPS.2011.6088966},
  doi          = {10.1109/SIPS.2011.6088966},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/sips/HsuC11a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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