BibTeX record conf/sips/ChangCS06

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@inproceedings{DBLP:conf/sips/ChangCS06,
  author       = {Hoseok Chang and
                  Junho Cho and
                  Wonyong Sung},
  title        = {Performance Evaluation of an {SIMD} Architecture with a Multi-bank
                  Vector Memory Unit},
  booktitle    = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
                  2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada},
  pages        = {71--76},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/SIPS.2006.352558},
  doi          = {10.1109/SIPS.2006.352558},
  timestamp    = {Sun, 21 May 2017 00:20:17 +0200},
  biburl       = {https://dblp.org/rec/conf/sips/ChangCS06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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