BibTeX record conf/sies/DiemerTE12

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@inproceedings{DBLP:conf/sies/DiemerTE12,
  author       = {Jonas Diemer and
                  Daniel Thiele and
                  Rolf Ernst},
  title        = {Formal worst-case timing analysis of Ethernet topologies with strict-priority
                  and {AVB} switching},
  booktitle    = {7th {IEEE} International Symposium on Industrial Embedded Systems,
                  {SIES} 2012, Karlsruhe, Germany, June 20-22, 2012},
  pages        = {1--10},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/SIES.2012.6356564},
  doi          = {10.1109/SIES.2012.6356564},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/sies/DiemerTE12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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