FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study.

Helena Krupnova Christian Rabedaoro Gabriele Saucier FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study. 128-133 1999 IEEE International Workshop on Rapid System Prototyping http://computer.org/proceedings/rsp/0246/02460128abs.htm db/conf/rsp/rsp1999.html#KrupnovaRS99