BibTeX record conf/rsp/ChattopadhyaySZLAM06

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@inproceedings{DBLP:conf/rsp/ChattopadhyaySZLAM06,
  author       = {Anupam Chattopadhyay and
                  Arnab Sinha and
                  Diandian Zhang and
                  Rainer Leupers and
                  Gerd Ascheid and
                  Heinrich Meyr},
  title        = {Integrated Verification Approach during ADL-Driven Processor Design},
  booktitle    = {17th {IEEE} International Workshop on Rapid System Prototyping {(RSP}
                  2006), 14-16 June 2006, Chania, Crete, Greece},
  pages        = {110--118},
  publisher    = {{IEEE} Computer Society},
  year         = {2006},
  url          = {https://doi.org/10.1109/RSP.2006.21},
  doi          = {10.1109/RSP.2006.21},
  timestamp    = {Thu, 23 Mar 2023 23:57:56 +0100},
  biburl       = {https://dblp.org/rec/conf/rsp/ChattopadhyaySZLAM06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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