Compile-time dynamic voltage scaling settings: opportunities and limits.

Fen Xie Margaret Martonosi Sharad Malik Compile-time dynamic voltage scaling settings: opportunities and limits. 49-62 2003 conf/pldi/2003 PLDI http://doi.acm.org/10.1145/781131.781138 db/conf/pldi/pldi2003.html#XieMM03