A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation.

Yoshiyasu Ogasawara Norito Kato Masanori Yamato Mikiko Sato Koichi Sasada Kaname Uchikura Mitaro Namiki Hironori Nakajo A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. 447-453 2005 conf/pdpta/2005-2 PDPTA db/conf/pdpta/pdpta2005-2.html#OgasawaraKYSSUNN05