Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number.

Hironori Nakajo Masanori Yamato Shoji Kawahara Norito Kato Koichi Sasada Mikiko Sato Mitaro Namiki Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. 1775-1781 2003 conf/pdpta/2003-4 PDPTA db/conf/pdpta/pdpta2003-4.html#NakajoYKKSSN03