BibTeX
@inproceedings{DBLP:conf/patmos/ZuberGRS05,
author = {Paul Zuber and
Peter Gritzmann and
Michael Ritter and
Walter Stechele},
title = {The Optimal Wire Order for Low Power CMOS},
booktitle = {PATMOS},
year = {2005},
pages = {674-683},
ee = {http://dx.doi.org/10.1007/11556930_69},
crossref = {DBLP:conf/patmos/2005},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
@proceedings{DBLP:conf/patmos/2005,
editor = {Vassilis Paliouras and
Johan Vounckx and
Diederik Verkest},
title = {Integrated Circuit and System Design, Power and Timing Modeling,
Optimization and Simulation, 15th International Workshop,
PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings},
booktitle = {PATMOS},
publisher = {Springer},
series = {Lecture Notes in Computer Science},
volume = {3728},
year = {2005},
isbn = {3-540-29013-3},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2005-09-01 by Michael Ley (ley@uni-trier.de)