Alexandre Verle Xavier Michel Philippe Maurine Nadine Azémard Daniel Auvergne CMOS Gate Sizing under Delay Constraint. 60-69 http://springerlink.metapress.com/openurl.asp?genre=article&issn=0302-9743&volume=2799&spage=60 2003 conf/patmos/2003 PATMOS db/conf/patmos/patmos2003.html#VerleMMAA03