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Pilar Parra Antonio J. Acosta Manuel Valencia Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. 448-457 2002 conf/patmos/2002 PATMOS http://springerlink.metapress.com/openurl.asp?genre=article&issn=0302-9743&volume=2451&spage=0448 db/conf/patmos/patmos2002.html#ParraAV02