BibTeX record conf/patmos/MinanaHGLCL06

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@inproceedings{DBLP:conf/patmos/MinanaHGLCL06,
  author       = {Guadalupe Mi{\~{n}}ana and
                  Jos{\'{e}} Ignacio Hidalgo and
                  Oscar Garnica and
                  Juan Lanchares and
                  Jos{\'{e}} Manuel Colmenar and
                  Sonia L{\'{o}}pez},
  editor       = {Johan Vounckx and
                  Nadine Az{\'{e}}mard and
                  Philippe Maurine},
  title        = {A Technique to Reduce Static and Dynamic Power of Functional Units
                  in High-Performance Processors},
  booktitle    = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
                  and Simulation, 16th International Workshop, {PATMOS} 2006, Montpellier,
                  France, September 13-15, 2006, Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {4148},
  pages        = {514--523},
  publisher    = {Springer},
  year         = {2006},
  url          = {https://doi.org/10.1007/11847083\_50},
  doi          = {10.1007/11847083\_50},
  timestamp    = {Sat, 09 Apr 2022 12:43:17 +0200},
  biburl       = {https://dblp.org/rec/conf/patmos/MinanaHGLCL06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}