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BibTeX record conf/patmos/DabiriNPS07
@inproceedings{DBLP:conf/patmos/DabiriNPS07, author = {Foad Dabiri and Ani Nahapetian and Miodrag Potkonjak and Majid Sarrafzadeh}, editor = {Nadine Az{\'{e}}mard and Lars J. Svensson}, title = {Soft Error-Aware Power Optimization Using Gate Sizing}, booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, {PATMOS} 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {4644}, pages = {255--267}, publisher = {Springer}, year = {2007}, url = {https://doi.org/10.1007/978-3-540-74442-9\_25}, doi = {10.1007/978-3-540-74442-9\_25}, timestamp = {Tue, 14 May 2019 10:00:54 +0200}, biburl = {https://dblp.org/rec/conf/patmos/DabiriNPS07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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