@inproceedings{DBLP:conf/patmos/DabiriNPS07,
author = {Foad Dabiri and
Ani Nahapetian and
Miodrag Potkonjak and
Majid Sarrafzadeh},
title = {Soft Error-Aware Power Optimization Using Gate Sizing},
booktitle = {PATMOS},
year = {2007},
pages = {255-267},
ee = {http://dx.doi.org/10.1007/978-3-540-74442-9_25},
crossref = {DBLP:conf/patmos/2007},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
@proceedings{DBLP:conf/patmos/2007,
editor = {Nadine Az{\'e}mard and
Lars J. Svensson},
title = {Integrated Circuit and System Design. Power and Timing Modeling,
Optimization and Simulation, 17th International Workshop,
PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings},
booktitle = {PATMOS},
publisher = {Springer},
series = {Lecture Notes in Computer Science},
volume = {4644},
year = {2007},
isbn = {978-3-540-74441-2},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
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