Peter Celinski Derek Abbott Sorin Cotofana Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic. 899-906 http://springerlink.metapress.com/openurl.asp?genre=article&issn=0302-9743&volume=3254&spage=899 2004 conf/patmos/2004 PATMOS db/conf/patmos/patmos2004.html#CelinskiAC04