@inproceedings{DBLP:conf/patmos/CalderonDJRMOV05,
author = {Alejandro Mill{\'a}n Calder{\'o}n and
Manuel Jes{\'u}s Bellido D\'{\i}az and
Jorge Juan-Chico and
Paulino Ruiz-de-Clavijo and
David Guerrero Martos and
Enrique Ost{\'u}a and
Julian Viejo},
title = {Application of Internode Model to Global Power Consumption
Estimation in SCMOS Gates},
booktitle = {PATMOS},
year = {2005},
pages = {337-347},
ee = {http://dx.doi.org/10.1007/11556930_35},
crossref = {DBLP:conf/patmos/2005},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
@proceedings{DBLP:conf/patmos/2005,
editor = {Vassilis Paliouras and
Johan Vounckx and
Diederik Verkest},
title = {Integrated Circuit and System Design, Power and Timing Modeling,
Optimization and Simulation, 15th International Workshop,
PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings},
booktitle = {PATMOS},
publisher = {Springer},
series = {Lecture Notes in Computer Science},
volume = {3728},
year = {2005},
isbn = {3-540-29013-3},
bibsource = {DBLP, http://dblp.uni-trier.de}
}