![](https://dblp.uni-trier.de/img/logo.ua.320x120.png)
![](https://dblp.uni-trier.de/img/dropdown.dark.16x16.png)
![](https://dblp.uni-trier.de/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
default search action
BibTeX record conf/patmos/Beerel06
@inproceedings{DBLP:conf/patmos/Beerel06, author = {Peter A. Beerel}, editor = {Johan Vounckx and Nadine Az{\'{e}}mard and Philippe Maurine}, title = {Asynchronous Design for High-Speed and Low-Power Circuits}, booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, {PATMOS} 2006, Montpellier, France, September 13-15, 2006, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {4148}, pages = {669}, publisher = {Springer}, year = {2006}, url = {https://doi.org/10.1007/11847083\_66}, doi = {10.1007/11847083\_66}, timestamp = {Tue, 14 May 2019 10:00:54 +0200}, biburl = {https://dblp.org/rec/conf/patmos/Beerel06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
![](https://dblp.uni-trier.de/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.