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BibTeX record conf/norchip/SeyediACUV12
@inproceedings{DBLP:conf/norchip/SeyediACUV12, author = {Azam Seyedi and Adri{\`{a}} Armejach and Adri{\'{a}}n Cristal and Osman S. Unsal and Mateo Valero}, title = {Novel {SRAM} bias control circuits for a low power {L1} data cache}, booktitle = {{NORCHIP} 2012, Copenhagen, Denmark, November 12-13, 2012}, pages = {1--6}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/NORCHP.2012.6403113}, doi = {10.1109/NORCHP.2012.6403113}, timestamp = {Wed, 16 Oct 2019 14:14:56 +0200}, biburl = {https://dblp.org/rec/conf/norchip/SeyediACUV12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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