BibTeX record conf/newcas/PosserFWR12

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@inproceedings{DBLP:conf/newcas/PosserFWR12,
  author       = {Gracieli Posser and
                  Guilherme Flach and
                  Gustavo Wilke and
                  Ricardo Reis},
  title        = {Transistor sizing and gate sizing using geometric programming considering
                  delay minimization},
  booktitle    = {10th {IEEE} International {NEWCAS} Conference, Montreal, QC, Canada,
                  June 17-20, 2012},
  pages        = {85--88},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/NEWCAS.2012.6328962},
  doi          = {10.1109/NEWCAS.2012.6328962},
  timestamp    = {Tue, 22 Oct 2019 15:21:17 +0200},
  biburl       = {https://dblp.org/rec/conf/newcas/PosserFWR12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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