BibTeX record conf/newcas/Chang16

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@inproceedings{DBLP:conf/newcas/Chang16,
  author       = {Yun{-}Nan Chang},
  title        = {Design of an area-efficient partial-sum architecture for polar decoders
                  based on new matrix generator},
  booktitle    = {14th {IEEE} International New Circuits and Systems Conference, {NEWCAS}
                  2016, Vancouver, BC, Canada, June 26-29, 2016},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/NEWCAS.2016.7604803},
  doi          = {10.1109/NEWCAS.2016.7604803},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/newcas/Chang16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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