BibTeX record conf/nanoarch/WuCWTSTZ15

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@inproceedings{DBLP:conf/nanoarch/WuCWTSTZ15,
  author       = {Bi Wu and
                  Yuanqing Cheng and
                  Ying Wang and
                  Aida Todri{-}Sanial and
                  Guangyu Sun and
                  Lionel Torres and
                  Weisheng Zhao},
  title        = {An architecture-level cache simulation framework supporting advanced
                  {PMA} {STT-MRAM}},
  booktitle    = {Proceedings of the 2015 {IEEE/ACM} International Symposium on Nanoscale
                  Architectures, {NANOARCH} 2015, Boston, MA, USA, July 8-10, 2015},
  pages        = {7--12},
  publisher    = {{IEEE} Computer Society},
  year         = {2015},
  url          = {https://doi.org/10.1109/NANOARCH.2015.7180576},
  doi          = {10.1109/NANOARCH.2015.7180576},
  timestamp    = {Thu, 23 Mar 2023 23:57:45 +0100},
  biburl       = {https://dblp.org/rec/conf/nanoarch/WuCWTSTZ15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}