BibTeX record conf/mwscas/PoloJMR12

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@inproceedings{DBLP:conf/mwscas/PoloJMR12,
  author       = {Agenor Polo and
                  Manuel Jim{\'{e}}nez and
                  David Marquez and
                  Domingo Rodr{\'{\i}}guez},
  title        = {An address generator approach to the hardware implementation of a
                  scalable Pease {FFT} core},
  booktitle    = {55th {IEEE} International Midwest Symposium on Circuits and Systems,
                  {MWSCAS} 2012, Boise, ID, USA, August 5-8, 2012},
  pages        = {832--835},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/MWSCAS.2012.6292149},
  doi          = {10.1109/MWSCAS.2012.6292149},
  timestamp    = {Tue, 29 Nov 2022 17:32:48 +0100},
  biburl       = {https://dblp.org/rec/conf/mwscas/PoloJMR12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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