A Scalable Symbolic Simulator for Verilog RTL.

Sasidhar Sunkari Supratik Chakraborty Vivekananda M. Vedula Kailasnath Maneparambil A Scalable Symbolic Simulator for Verilog RTL. 51-59 2007 MTV http://dx.doi.org/10.1109/MTV.2007.13 conf/mtv/2007 db/conf/mtv/mtv2007.html#SunkariCVM07