BibTeX record: conf/mtdt/VollrathSGSJ06

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@inproceedings{DBLP:conf/mtdt/VollrathSGSJ06,
  author    = {J{\"{o}}rg E. Vollrath and
               J{\"{u}}rg Schwizer and
               Marcin Gnat and
               Ralf Schneider and
               Bret Johnson},
  title     = {{DDR2} {DRAM} Output Timing Optimization},
  booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
               Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
  year      = {2006},
  pages     = {49--54},
  crossref  = {DBLP:conf/mtdt/2006},
  url       = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2006.9},
  doi       = {10.1109/MTDT.2006.9},
  timestamp = {Tue, 23 Sep 2014 18:49:35 +0200},
  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/mtdt/VollrathSGSJ06},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/mtdt/2006,
  title     = {14th {IEEE} International Workshop on Memory Technology, Design, and
               Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
  year      = {2006},
  publisher = {{IEEE} Computer Society},
  isbn      = {0-7695-2572-5},
  timestamp = {Tue, 23 Sep 2014 18:49:35 +0200},
  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/mtdt/2006},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}