author    = {T. Devoivre and
               M. Lunenborg and
               C. Julien and
               J.-P. Carrere and
               P. Ferreira and
               W. J. Toren and
               A. VandeGoor and
               P. Gayet and
               T. Berger and
               O. Hinsinger and
               P. Vannier and
               Y. Trouiller and
               Y. Rody and
               P.-J. Goirand and
               R. Palla and
               I. Thomas and
               F. Guyader and
               D. Roy and
               B. Borot and
               N. Planes and
               S. Naudet and
               F. Pico and
               D. Duca and
               F. Lalanne and
               D. Heslinga and
               M. Haond},
  title     = {Validated 90nm CMOS Technology Platform with Low-k Copper
               Interconnects for Advanced System-on-Chip (SoC)},
  booktitle = {MTDT},
  year      = {2002},
  pages     = {157-162},
  ee        = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2002.1029778},
  crossref  = {DBLP:conf/mtdt/2002},
  bibsource = {DBLP, http://dblp.uni-trier.de}
  title     = {10th IEEE International Workshop on Memory Technology, Design,
               and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor,
  booktitle = {MTDT},
  publisher = {IEEE Computer Society},
  year      = {2002},
  isbn      = {0-7695-1617-3},
  bibsource = {DBLP, http://dblp.uni-trier.de}